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Tegra is a system on a chip (SoC) series developed by for mobile devices such as , personal digital assistants, and mobile Internet devices. The Tegra integrates an central processing unit (CPU), graphics processing unit (GPU), northbridge, southbridge, and memory controller onto one package. Early Tegra SoCs are designed as efficient multimedia processors. The Tegra-line evolved to emphasize performance for gaming and applications without sacrificing power efficiency, before taking a drastic shift in direction towards platforms that provide vehicular automation with the applied " " brand name on reference boards and its semiconductors; and with the " " brand name for boards adequate for within e.g. robots or drones, and for various smart high level automation purposes.


History
The Tegra APX 2500 was announced on February 12, 2008. The Tegra 6xx product line was revealed on June 2, 2008, and the APX 2600 was announced in February 2009. The APX chips were designed for smartphones, while the Tegra 600 and 650 chips were intended for and mobile Internet devices (MID).

The first product to use the Tegra was 's media player in September 2009, followed by the M1. Microsoft's was the first cellular phone to use the Tegra; however, the phone did not have an app store, so the Tegra's power did not provide much advantage. In September 2008, Nvidia and announced that they would produce a version of the Opera 9.5 browser optimized for the Tegra on and . At Mobile World Congress 2009, Nvidia introduced its port of 's Android to the Tegra.

On January 7, 2010, Nvidia officially announced and demonstrated its next generation Tegra system-on-a-chip, the Nvidia Tegra 250, at Consumer Electronics Show 2010. Nvidia primarily supports Android on Tegra 2, but booting other ARM-supporting operating systems is possible on devices where the is accessible. Tegra 2 support for the Ubuntu Linux distribution was also announced on the Nvidia developer forum.

Nvidia announced the first quad-core SoC at the February 2011 Mobile World Congress event in Barcelona. Though the chip was codenamed Kal-El, it is now branded as Tegra 3. Early benchmark results show impressive gains over Tegra 2, and the chip was used in many of the tablets released in the second half of 2011.

In January 2012, announced that had selected the Tegra 3 processor for its In-Vehicle Infotainment systems and digital instruments display. The processor will be integrated into Audi's entire line of vehicles worldwide, beginning in 2013. The process is ISO 26262-certified.

In summer of 2012 began shipping the Model S all electric, high performance sedan, which contains two NVIDIA Tegra 3D Visual Computing Modules (VCM). One VCM powers the 17-inch infotainment system, and one drives the 12.3-inch all digital instrument cluster."

In March 2015, Nvidia announced the Tegra X1, the first SoC to have a graphics performance of 1 teraflop. At the announcement event, Nvidia showed off 4 "Elemental" demo, running on a Tegra X1.

On October 20, 2016, Nvidia announced that the hybrid video game console will be powered by Tegra hardware. On March 15, 2017, TechInsights revealed the Nintendo Switch is powered by a custom Tegra X1 (model T210), with lower clockspeeds.


Models

Tegra APX
Tegra APX 2500
  • Processor: ARM11 600 MHz MPCore (originally GeForce ULV)
    • Suffix: APX (formerly CSX)
  • Memory: NOR or NAND flash, Mobile DDR
  • Graphics: Image processor (FWVGA 854×480 pixels)
    • Up to 12 camera support
    • LCD controller supports resolutions up to 1280×1024
  • Storage: IDE for SSD
  • Video codecs: up to 720p MPEG-4 AVC/H.264 and VC-1 decoding
  • Includes ULV support for 2.0, Direct3D Mobile, and programmable shaders
  • Output: , , , , stereo jack, USB
Tegra APX 2600
  • Enhanced NAND flash
  • Video codecs:
    • 720p H.264 Baseline Profile encode or decode
    • 720p VC-1/WMV9 Advanced Profile decode
    • D-1 MPEG-4 Simple Profile encode or decode


Tegra 6xx
Tegra 600
  • Targeted for GPS segment and automotive
  • Processor: ARM11 700 MHz MPCore
  • Memory: (, 166 MHz)
  • SXGA, HDMI, USB, stereo jack
  • HD camera 720p
Tegra 650
  • Targeted for GTX of handheld and notebook
  • Processor: ARM11 800 MHz MPCore
  • (, 200 MHz)
  • Less than 1 watt envelope
  • HD image processing for advanced digital still camera and HD camcorder functions
  • Display supports 1080p at 24 frame/s, HDMI v1.3, WSXGA+ LCD and CRT, and NTSC/PAL TV output
  • Direct support for Wi-Fi, disk drives, keyboard, mouse, and other peripherals
  • A complete board support package (BSP) to enable fast time to market for Windows Mobile-based designs


Tegra 2
The second generation Tegra SoC has a dual-core ARM Cortex-A9 CPU, an ultra low power (ULP) GeForce GPU, a 32-bit memory controller with either LPDDR2-600 or DDR2-667 memory, a 32 KB/32 KB L1 cache per core and a shared 1 MB L2 cache. Tegra 2's Cortex A9 implementation does not include ARM's SIMD extension, . There is a version of the Tegra 2 SoC supporting 3D displays; this SoC uses a higher clocked CPU and GPU.

The Tegra 2 video decoder is largely unchanged from the original Tegra and has limited support for HD formats. The lack of support for high-profile H.264 is particularly troublesome when using online video streaming services.

Common features:

  • CPU cache: L1: 32 KB instruction + 32 KB data, L2: 1 MB
  • 40 nm semiconductor technology

1 : : Texture mapping units : Render output units


Devices
Model S 2012~2017 and Model X 2015~2017 instrument cluster (IC) Nvidia inside: Hands on with Audi, Lamborghini, and Tesla by Megan Geuss in May 2014 Processors Analysis and Count in May 2013


Tegra 3
NVIDIA's Tegra 3 ( "") is functionally a SoC with a quad-core ARM Cortex-A9 MPCore CPU, but includes a fifth "companion" core in what Nvidia refers to as a "variable SMP architecture". While all cores are Cortex-A9s, the companion core is manufactured with a low-power silicon process. This core operates transparently to applications and is used to reduce power consumption when processing load is minimal. The main quad-core portion of the CPU powers off in these situations.

Tegra 3 is the first Tegra release to support ARM's SIMD extension, .

The GPU in Tegra 3 is an evolution of the Tegra 2 GPU, with 4 additional pixel shader units and higher clock frequency. It can also output video up to 2560×1600 resolution and supports 1080p MPEG-4 AVC/h.264 40 Mbit/s High-Profile, VC1-AP, and simpler forms of MPEG-4 such as DivX and Xvid.

The Tegra 3 was released on November 9, 2011.

Common features:

  • CPU cache: L1: 32 KB instruction + 32 KB data, L2: 1 MB
  • 40 nm LPG semiconductor technology by

1 : : Texture mapping units : Render output units


Devices


Tegra 4
The Tegra 4 ( "") was announced on January 6, 2013, and is a SoC with a quad-core CPU, but includes a fifth low-power Cortex A15 companion core which is invisible to the OS and performs background tasks to save power. This power-saving configuration is referred to as "variable SMP architecture" and operates like the similar configuration in Tegra 3.

The GeForce GPU in Tegra 4 is again an evolution of its predecessors. However, numerous feature additions and efficiency improvements were implemented. The number of processing resources was dramatically increased, and clock rate increased as well. In 3D tests, the Tegra 4 GPU is typically several times faster than that of Tegra 3. Additionally, the Tegra 4 video processor has full support for hardware decoding and encoding of video (up to 1080p 60 Mbit/s @ 60fps).

Along with Tegra 4, Nvidia also introduced i500, an optional software modem based on Nvidia's acquisition of , which can be reprogrammed to support new network standards. It supports category 3 (100 Mbit/s) LTE but will later be updated to Category 4 (150 Mbit/s).

Common features:

  • CPU cache: L1: 32 KB instruction + 32 KB data, L2: 2 MB
  • 28 nm HPL semiconductor technology

1 : : (pairs 1x TMU and 1x ROP)


Devices


Tegra 4i
The Tegra 4i ( "") was announced on February 19, 2013. With hardware support for the same audio and video formats, but using Cortex-A9 cores instead of Cortex-A15, the Tegra 4i is a low-power variant of the Tegra 4 and is designed for phones and tablets. Unlike its Tegra 4 counterpart, the Tegra 4i also integrates the  i500 LTE/ baseband processor onto the same die.

Common features:

  • 28 nm HPM semiconductor technology
  • CPU cache: L1: 32 KB instruction + 32 KB data, L2: 1 MB

1 : : (pairs 1x TMU and 1x ROP)


Devices


Tegra K1
's Tegra K1 (codenamed "Logan") features ARM Cortex-A15 cores in a 4+1 configuration similar to Tegra 4, or Nvidia's 64-bit dual-core processor as well as a Kepler graphics processing unit with support for Direct3D 12, OpenGL ES 3.1, CUDA 6.5, /OpenGL 4.5, and Vulkan. Nvidia claims that it outperforms both the Xbox 360 and the PS3, whilst consuming significantly less power.

Support Adaptive Scalable Texture Compression.

In late April 2014, Nvidia shipped the "Jetson TK1" development board containing a Tegra K1 SoC and running Ubuntu Linux.

  • Processor:
  • GPU consisting of 192 ALUs using Kepler technology
  • 28 nm HPM process
  • Released in Q2 2014
  • Power consumption: 8 watts

1 Unified Shaders : Texture mapping units : Render output units
2 ARM Large Physical Page Extension (LPAE) supports 1  (240 bytes).
The 8  limitation is part-specific.


Devices

In December 2015, the web page of wccftech.com published an article stating that Tesla is going to use a Tegra K1 based design derived from the template of the Nvidia Visual Computing Module (VCM) for driving the infotainment systems and providing visual driving aid in the respective vehicle models of that time. Exclusive: The Tesla AutoPilot – An In-Depth Look At The Technology Behind the Engineering Marvel by Usman Pirzada on Dec 3, 2015 This news has, as of now, found no similar successor or other clear confirmation later on in any other place on such a combination of a multimedia with an auto pilot system for these vehicle models.


Tegra X1
Released in 2015, Nvidia's Tegra X1 (codenamed "") features two CPU clusters, one with four ARM Cortex-A57 cores and the other with four ARM Cortex-A53 cores, as well as a Maxwell-based graphics processing unit. It supports Adaptive Scalable Texture Compression. Only one cluster of cores can be active at once, with the cluster switch being handled by software on the BPMP-L. Devices utilizing the Tegra X1 have only been seen to utilize the cluster with the more powerful ARM Cortex-A57 cores. The other cluster with four ARM Cortex-A53 cores cannot be accessed without first powering down the Cortex-A57 cores (both clusters must be in the CC6 off state).Tegra_X1_TRM_DP07225001_v1.0.pdf Nvidia has removed the ARM Cortex-A53 cores from later versions of technical documentation, implying that they have been removed from the die. The Tegra X1 was found to be vulnerable to a Fault Injection (FI) voltage glitching attack, which allowed for arbitrary code execution and homebrew software on the devices it was implemented in.
(2021). 9781665436731

A revision (codenamed "") with greater power efficiency, known officially as Tegra X1+ was released in 2019, fixing the Fusée Gelée exploit. It's also known as T214 and T210B01.

  • : ARMv8 ARM Cortex-A57 quad-core (64-bit) + (unused?) ARM Cortex-A53 quad-core (64-bit)
  • : Maxwell-based 256 core GPU (Jetson Nano: only 128 cores)
  • MPEG-4 VP8 encoding/decoding & VP9 decoding support (Jetson Nano: encoders are H.265, H.264/Stereo, VP8, ; decoders are H.265, H.264/Stereo, VP8, VP9, VC-1, MPEG-2, JPEG)
  • 20 nm process for the Tegra X1
  • TSMC 16 nm process for the Tegra X1+.
  • TDP:
    • T210: 15 W, with average power consumption less than 10 W
    • Jetson Nano: 10 W (mode 0); mode 1: 5W (only 2 CPU cores @ 918 MHz, GPU @ 640 MHz)

TM660M-A24x 1.4 GHz
Cortex-A57 +
4x 1.0 GHz
Cortex-A53
921 MHz
(128:16:16)
236472LPDDR3?
LPDDR4
4 GBMarch 2019
1 CPU frequency may be clocked differently than the maximum validated by Nvidia at the OEM's discretion
2 Unified Shaders : Texture mapping units : Render output units
3 Maximum validated amount of memory, implementation is board specific
4 Maximum validated memory bandwidth, implementation is board specific


Devices
TM670D-A1Nvidia Shield Android TV (2015)
TM670M-A2Nvidia Shield Android TV (2017)
TM660M-A2Jetson Nano 4 GB, Jetson Nano 2 GB
TM671D-A2Google
TX1 development board,
TM675M-A1Nvidia Shield Android TV (2019)


Tegra X2
Nvidia's Tegra X2 NVIDIA Jetson TX2 Delivers Twice the Intelligence to the Edge by Dustin Franklin on March 7, 2017 at Nvidia Developer Blogs (codenamed "") features Nvidia' Https://developer.nvidia.com/embedded/dlc/jetson-tx2-module-data-sheet
The chips are made using process technology using 's 16 nm FinFET+ manufacturing process.

  • CPU: Nvidia Denver2 ARMv8 (64-bit) dual-core + ARMv8 ARM Cortex-A57 quad-core (64-bit)
  • RAM: up to 8 GB LPDDR4
  • GPU: Pascal-based, 256 cores; type: GP10B

1 Unified Shaders : Texture mapping units : Render output units (SM count)


Devices
Mercedes-Benz MBUX (infotainment system) NVIDIA Powers Mercedes-Benz MBUX, Its Next-Gen AI Cockpit by Danny Shapiro on January 9, 2018 via Nvidia company blogs
1 unit along with 1 GPU semiconductor is part of the ECU for "Tesla vision"
functionality in all Tesla vehicles since October 2016 Look inside Tesla's onboard Nvidia supercomputer for self-driving by Fred Lambert on May 22, 2017 Tesla Working With AMD on Self-Driving Car Processor by Joel Hruska on September 21, 2017
Skydio 2 (drone) Skydio's second-gen drone, a $1,000 self-flying action cam, sells out for 2019 by Stephen Shankland on October 2, 2019


Xavier
The Xavier Tegra SoC, named after the comic book character , was announced on 28 September 2016, and by March 2019, it had been released. It contains 7 billion transistors and 8 custom ARMv8 cores, a Volta GPU with 512 CUDA cores, an open sourced TPU (Tensor Processing Unit) called DLA (Deep Learning Accelerator). It is able to encode and decode 8K Ultra HD (7680×4320). Users can configure operating modes at 10 W, 15 W, and 30 W TDP as needed and the die size is 350 mm2. Nvidia confirmed the fabrication process to be 12 nm FinFET at CES 2018.

  • CPU: Nvidia custom Carmel ARMv8.2-A (64-bit), 8 cores 10-wide superscalar NVIDIA Drive Xavier SOC Detailed by Hassan Mujtaba on Jan 8, 2018 via WccfTech
  • GPU: Volta-based, 512 cores with 1.4 TFLOPS; type: GV11B
  • TSMC 12 nm, process
  • 20 TOPS DL and 160 @ 20 W; 30 TOPS DL @ 30 W (TOPS DL = Deep Learning Tera-Ops)
    • 20 TOPS DL via the GPU based tensor cores
    • 10 TOPS DL (INT8) via the DLA unit that shall achieve 5 TFLOPS (FP16)
  • 1.6 TOPS in the PVA unit (Programmable Vision Accelerator, for StereoDisparity/OpticalFlow/ImageProcessing)
  • 1.5 GPix/s in the ISP unit (Image Signal Processor, with native full-range HDR and tile processing support)
  • Video processor for 1.2 GPix/s encoding and 1.8 GPix/s decode including 8k video support
  • MIPI-CSI-3 with 16 lanes
  • 1 Gbit/s Ethernet
  • 10 Gbit/s Ethernet

1 : (SMs, TPCs, GPCs)


Devices
(Drive PX-series)
Nvidia Drive AGX Xavier Developer Kit
Nvidia Jetson AGX Xavier Developer Kit
Nvidia Clara AGX "Clara AGX is based on NVIDIA Xavier and NVIDIA Turing GPUs."
Bosch and designed Self Driving System
ZF ProAI

On the Linux Kernel Mailing List, a Tegra194 based development board with type ID "P2972-0000" got reported:

The board consists of the P2888 compute module and the P2822 baseboard. Linux Kernel Mailing List: (PATCH v3 7/7) arm64: tegra: Add device tree for the Tegra194 P2972-0000 board by Mikko Perttunen on Feb 15 2018


Orin
Nvidia announced the next-gen SoC codename on March 27, 2018, at GPU Technology Conference 2018.
It contains 17 billion transistors and 12 ARM Hercules cores and is capable of 200 INT8 TOPs @ 65W.
The Drive AGX Orin board system family was announced on December 18, 2019, at GTC China 2019.

Nvidia has sent papers to the press documenting that the known (from Xavier series) clock and voltage scaling on the semiconductors

and by pairing multiple such chips a wider range of application can be realized with the thus resulting board concepts.
In early 2021, Nvidia announced the Chinese vehicle company NIO will be using an Orin-based chip in their cars.

The so far published specifications for Orin are:

  • CPU: 12× Arm Cortex-A78AE ( Hercules) ARMv8.2-A (64-bit)
  • GPU: Https://blogs.nvidia.com/blog/2021/01/09/nio-selects-nvidia-intelligent-electric-vehicles/ 8192 cores / 4 SoCs = 2048 cores / SoC cores and 64 tensor cores1; "with up to 131 Sparse TOPs
    of INT8 Tensor compute, and up to 5.32 FP32 TFLOPs of CUDA compute."
    • 5.3 CUDA TFLOPs (FP32)
    • 10.6 CUDA TFLOPs (FP16)
  • Samsung 8 nm process
  • 275 TOPS (INT8) DL
    • 170 TOPS DL (INT8) via the GPU
    • 105 TOPS DL (INT8) via the 2x 2.0 units (, Deep Learning Accelerator)
  • 85 TOPS DL (FP16)
  • 5 TOPS in the PVA v2.0 unit (Programmable Vision Accelerator for Feature Tracking)
  • 1.85 GPix/s in the ISP unit (Image Signal Processor, with native full-range HDR and tile processing support)
  • Video processor for ? GPix/s encoding and ? GPix/s decode
  • 4× 10 Gbit/s Ethernet, 1× 1 Gbit/s Ethernet
1 Orin uses the double-rate tensor cores in the A100, not the standard tensor cores in consumer Ampere GPUs.

Nvidia announced the latest member of the family, "Orin Nano" in September 2022 at the GPU Technology Conference 2022.

The Orin product line now features SoC and SoM (System-On-Module) based on the core Orin design and scaled for different uses from 60W all the way down to 5W. While less is known about the exact SoC's that are being manufactured, Nvidia has publicly shared detailed technical specifications about the entire Jetson Orin SoM product line. These module specifications illustrate how Orin scales providing insight into future devices that contain an Orin derived SoC.

1 : : (SMs, TPCs, GPCs)


Devices
Nvidia Jetson Orin NXmid-power SODIMM-form factor Orin-series module, available only as standalone module;
pin-compatible with Xavier NX carrier
Nvidia Jetson Orin Nanolow-power, cost-effective SODIMM-form factor Orin-series module, available
as standalone module or devkit; intended for entry-level usage
Nvidia DRIVE AGX Orinused in automotive ADAS applications. 1×Orin 12×A78AE 32GB LPDDR5 @100W, 167+87 INT8 TOPS
Nio Adambuilt from 4× Nvidia Drive Orin, totals to 48 CPU cores and 8,192 CUDA cores;
for use in vehicles ET7 in March 2022 and ET5 in September 2022


Grace
The CPU is an NVIDIA-developed V2 ( Demeter) CPU platform, targeted at large-scale AI and HPC applications, available within several NVIDIA products. The NVIDIA OVX platform combines the Grace Superchip (two Grace dies on one board) with desktop NVIDIA GPUs in a server form-factor, while the NVIDIA HGX platform is available with either the Grace Superchip or the Grace Hopper Superchip.

The latter is an HPC platform in of itself, combining a Grace CPU with a Hopper-based GPU, announced by NVIDIA on March 22, 2022.

Kernel patchsets indicate that a single Grace CPU is also known as T241, placing it under the Tegra SoC branding, despite the chip itself not including a GPU (a referenced T241 patchset cites impact to "NVIDIA server platforms that use more than two T241 chips...interconnected," pointing to the Grace Superchip design).

T241Grace - 72x

V2 cores
(ARMv9)
L1: 64 KB I-cache
+ 64 KB D-cache
per core
L2: 1 MB per core
L3: 117 MB shared
3.551LPDDR5X
ECC
Up to
480 GB1
?500 GB/sH2 2023
1Figures cut in half from full Grace Superchip specification


Atlan
Nvidia announced the next-gen SoC codename Atlan on April 12, 2021, at GPU Technology Conference 2021.

Nvidia announced the cancellation of Atlan on September 20, 2022, and their next SoC will be Thor.

Functional units known so far are:

  • Grace Next CPU
  • Ada Lovelace GPU
  • Bluefield DPU (Data Processing Unit)
  • other Accelerators
  • Security Engine
  • Functional Safety Island
  • On-Chip-Memory
  • External Memory Interface(s)
  • High-Speed-IO Interfaces

T254?Grace-Next
(?/?)
Ada
Lovelace
????>1000????Cancelled


Thor
Nvidia announced the next-gen SoC codename Thor on September 20, 2022, at GPU Technology Conference 2022, replacing the cancelled Atlan.

A patchset adding support for Tegra264 to mainline Linux was submitted May 5, 2023, likely indicating initial support for Thor.

The V3AE (Poseidon-AE) CPU is built to deliver maximum performance for automotive applications, central compute and machine learning (ML) workloads.

T264?14x

V3AE
(2.6 GHz)
Blackwell2560:96:?
(20, 10, 3)
1575 MHz8.0645001035LPDDR5X128 GB256-bit273 GB/s2025


Devices


Comparison
+ ! colspan="2"Generation !Tegra 2
(Ventana) !Tegra 3
(Kal-El) !Tegra 4
(Wayne) !Tegra 4i
(Grey) ! colspan="2"
Tegra K1
(Logan) !Tegra X1
(Erista) !TegraX1+
(Mariko) !Tegra X2
(Parker) !Tegra
Xavier !Tegra
Orin !Tegra
Thor
* -based Vec4: + . Since Kepler, Unified shaders are used.


Software support

FreeBSD
supports a number of different Tegra models and generations, ranging from Tegra K1, to Tegra 210.


Linux
Nvidia distributes proprietary device drivers for Tegra through and as part of its "Linux for Tegra" (formerly "L4T") development kit, also Nvidia provides JetPack SDK with "Linux for Tegra" and other tools with it. The newer and more powerful devices of the Tegra family are now supported by Nvidia's own Linux distribution. Vibrante comes with a larger set of Linux tools plus several Nvidia provided libraries for acceleration in the area of data processing and especially image processing for driving safety and automated driving up to the level of and neuronal networks that make e.g. heavy use of the CUDA capable accelerator blocks, and via can make use of the NEON vector extensions of the ARM cores.

, due to different "business needs" from that of their line of graphics cards, Nvidia and one of their Embedded Partners, Avionic Design GmbH from Germany, are also working on submitting open-source drivers for Tegra upstream to the mainline . Nvidia co-founder & CEO laid out the Tegra processor roadmap using Ubuntu Unity in GPU Technology Conference 2013.

By end of 2018 it is evident that Nvidia employees have contributed substantial code parts to make the T186 and T194 models run for HDMI display and audio with the upcoming official Linux kernel 4.21 in about Q1 2019. The affected software modules are the open source Nouveau and the closed source Nvidia graphics drivers along with the Nvidia proprietary CUDA interface.

As of May, 2022, NVIDIA has open-sourced their GPU kernel modules for both Jetson and desktop platforms, allowing all but proprietary userspace libraries to be open-source on Tegra platforms with official NVIDIA drivers starting with T234 (Orin).


QNX
The Drive PX2 board was announced with RTOS support at the April 2016 GPU Technology Conference.


Similar platforms
SoCs and platforms with comparable specifications (e.g. audio/video input, output and processing capability, connectivity, programmability, entertainment/embedded/automotive capabilities & certifications, power consumption) are:


See also


External links

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